Researching: What are the precise materials and tolerances in TSMC's 2nm process? {"question": "What are the precise materials and tolerances in TSMC's 2nm process?", "depth": "balanced", "max_iterations": null, "token_budget": null, "event": "ask_started", "logger": "marchwarden.cli", "level": "info", "timestamp": "2026-04-09T02:18:26.198498Z"} {"transport": "stdio", "server": "marchwarden-web-researcher", "event": "mcp_server_starting", "logger": "marchwarden.mcp", "level": "info", "timestamp": "2026-04-09T02:18:26.963097Z"} {"event": "Processing request of type CallToolRequest", "logger": "mcp.server.lowlevel.server", "level": "info", "timestamp": "2026-04-09T02:18:26.972484Z"} {"question": "What are the precise materials and tolerances in TSMC's 2nm process?", "depth": "balanced", "max_iterations": 5, "token_budget": 20000, "model_id": "claude-sonnet-4-6", "event": "research_started", "researcher": "web", "trace_id": "a4bb5b7a-61dd-446b-8c06-06c78de5fef7", "logger": "marchwarden.researcher.web", "level": "info", "timestamp": "2026-04-09T02:18:27.004492Z"} {"step": 1, "decision": "Beginning research: depth=balanced", "question": "What are the precise materials and tolerances in TSMC's 2nm process?", "context": "", "max_iterations": 5, "token_budget": 20000, "event": "start", "researcher": "web", "trace_id": "a4bb5b7a-61dd-446b-8c06-06c78de5fef7", "logger": "marchwarden.researcher.trace", "level": "info", "timestamp": "2026-04-09T02:18:27.004812Z"} {"step": 2, "decision": "Starting iteration 1/5", "tokens_so_far": 0, "event": "iteration_start", "researcher": "web", "trace_id": "a4bb5b7a-61dd-446b-8c06-06c78de5fef7", "logger": "marchwarden.researcher.trace", "level": "info", "timestamp": "2026-04-09T02:18:27.004904Z"} {"step": 7, "decision": "Starting iteration 2/5", "tokens_so_far": 1158, "event": "iteration_start", "researcher": "web", "trace_id": "a4bb5b7a-61dd-446b-8c06-06c78de5fef7", "logger": "marchwarden.researcher.trace", "level": "info", "timestamp": "2026-04-09T02:18:40.769568Z"} {"step": 14, "decision": "Starting iteration 3/5", "tokens_so_far": 11802, "event": "iteration_start", "researcher": "web", "trace_id": "a4bb5b7a-61dd-446b-8c06-06c78de5fef7", "logger": "marchwarden.researcher.trace", "level": "info", "timestamp": "2026-04-09T02:18:47.013233Z"} {"step": 19, "decision": "Token budget reached before iteration 4: 30249/20000", "event": "budget_exhausted", "researcher": "web", "trace_id": "a4bb5b7a-61dd-446b-8c06-06c78de5fef7", "logger": "marchwarden.researcher.trace", "level": "info", "timestamp": "2026-04-09T02:18:57.139804Z"} {"step": 20, "decision": "Beginning synthesis of gathered evidence", "evidence_count": 29, "iterations_run": 3, "tokens_used": 30249, "event": "synthesis_start", "researcher": "web", "trace_id": "a4bb5b7a-61dd-446b-8c06-06c78de5fef7", "logger": "marchwarden.researcher.trace", "level": "info", "timestamp": "2026-04-09T02:18:57.139984Z"} {"step": 21, "decision": "Parsed synthesis JSON successfully", "duration_ms": 77777, "event": "synthesis_complete", "researcher": "web", "trace_id": "a4bb5b7a-61dd-446b-8c06-06c78de5fef7", "logger": "marchwarden.researcher.trace", "level": "info", "timestamp": "2026-04-09T02:20:12.633197Z"} {"step": 40, "decision": "Research complete", "confidence": 0.42, "citation_count": 9, "gap_count": 5, "discovery_count": 4, "total_duration_sec": 109.056, "event": "complete", "researcher": "web", "trace_id": "a4bb5b7a-61dd-446b-8c06-06c78de5fef7", "logger": "marchwarden.researcher.trace", "level": "info", "timestamp": "2026-04-09T02:20:12.634189Z"} {"confidence": 0.42, "citations": 9, "gaps": 5, "discovery_events": 4, "tokens_used": 62620, "iterations_run": 3, "wall_time_sec": 105.62861347198486, "budget_exhausted": true, "event": "research_completed", "researcher": "web", "trace_id": "a4bb5b7a-61dd-446b-8c06-06c78de5fef7", "logger": "marchwarden.researcher.web", "level": "info", "timestamp": "2026-04-09T02:20:12.634324Z"} {"error": "[Errno 13] Permission denied: '/home/micro/.marchwarden/costs.jsonl'", "event": "cost_ledger_write_failed", "researcher": "web", "trace_id": "a4bb5b7a-61dd-446b-8c06-06c78de5fef7", "logger": "marchwarden.researcher.web", "level": "warning", "timestamp": "2026-04-09T02:20:12.634698Z"} {"event": "Processing request of type ListToolsRequest", "logger": "mcp.server.lowlevel.server", "level": "info", "timestamp": "2026-04-09T02:20:12.639617Z"} {"trace_id": "a4bb5b7a-61dd-446b-8c06-06c78de5fef7", "confidence": 0.42, "citations": 9, "tokens_used": 62620, "wall_time_sec": 105.62861347198486, "event": "ask_completed", "logger": "marchwarden.cli", "level": "info", "timestamp": "2026-04-09T02:20:12.967147Z"} ╭─────────────────────────────────── Answer ───────────────────────────────────╮ │ TSMC's 2nm (N2) process node, which began volume production in Q4 2025, │ │ introduces several key technical advances, though precise proprietary │ │ materials specifications and sub-angstrom tolerances are not publicly │ │ disclosed. What is publicly known: │ │ │ │ **Transistor Architecture:** N2 is TSMC's first node to use Gate-All-Around │ │ (GAA) nanosheet transistors, replacing the FinFET architecture used since │ │ 2011. The gate surrounds the silicon nanosheet channel on all sides, │ │ providing superior electrostatic control and reduced gate leakage compared │ │ to 3nm FinFETs [Sources 10, 13, 21]. │ │ │ │ **Process Node Dimensions (IEEE IRDS):** The 2nm node class is projected to │ │ have a contacted gate pitch of ~45nm and a tightest metal pitch of ~20nm, │ │ per IEEE International Roadmap for Devices and Systems (2021 update) [Source │ │ 16]. │ │ │ │ **Interconnects:** N2 features copper (Cu)-based redistribution layers │ │ (RDLs) with flat passivation and through-silicon vias (TSVs), co-optimized │ │ with 3DIC integration. Middle- and back-end-of-line (MEOL/BEOL) │ │ interconnects are included, with the densest SRAM macro ever reported at │ │ approximately 38 Mb/mm² [Sources 4, 21]. │ │ │ │ **Performance Metrics (vs. N3E):** 24–35% power reduction OR 15% performance │ │ improvement at iso-voltage; >1.15x transistor density improvement over N3 │ │ [Sources 10, 18, 21]. │ │ │ │ **Yield:** Initial yields reportedly ~70%, with some memory products │ │ exceeding 90%. A 6% yield improvement over baseline was reported in late │ │ 2024 [Sources 13, 14]. │ │ │ │ **Applications:** Designed for AI, mobile, and HPC applications. Key │ │ customers include Apple (A20 chip for iPhone 18 Pro) and NVIDIA [Sources 8, │ │ 14]. │ │ │ │ **Fab Locations:** Primary production in Hsinchu and Kaohsiung, Taiwan; a │ │ Kaohsiung 2nm facility expansion ceremony was held March 31, 2025 [Source │ │ 6]. │ │ │ │ **Specific proprietary materials** (e.g., exact dielectric compositions, │ │ gate oxide materials, metal liner chemistries, doping concentrations, and │ │ nanometer-level tolerances on nanosheet thickness/width) are not publicly │ │ disclosed by TSMC and were not found in the available evidence. │ ╰──────────────────────────────────────────────────────────────────────────────╯ Citations ┏━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━┓ ┃ # ┃ Title / Locator ┃ Excerpt ┃ Conf ┃ ┡━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━┩ │ 1 │ TSMC shares deep-dive details │ The new production node │ 0.95 │ │ │ about its cutting edge 2nm │ promises a 24 to 35% power │ │ │ │ process node at IEDM 2024 — │ reduction or 15% performance │ │ │ │ 35 percent less power or 15 │ improvement at the same │ │ │ │ percent more performance | │ voltage, and 1.15X higher │ │ │ │ Tom's Hardware │ transistor density than the │ │ │ │ https://www.tomshardware.com/ │ previous 3nm node. │ │ │ │ tech-industry/tsmc-shares-dee │ │ │ │ │ p-dive-details-about-its-cutt │ │ │ │ │ ing-edge-2nm-process-node-at- │ │ │ │ │ iedm-2024-35-percent-less-pow │ │ │ │ │ er-or-15-percent-more-perform │ │ │ │ │ ance │ │ │ ├─────┼───────────────────────────────┼────────────────────────────────┼───────┤ │ 2 │ IEDM 2024 – TSMC 2nm Process │ The paper states that the │ 0.95 │ │ │ Disclosure - TechInsights │ process delivers a 30% power │ │ │ │ https://library.techinsights. │ improvement or 15% performance │ │ │ │ com/public/hg-asset/f32a0f17- │ gain and >1.15x density versus │ │ │ │ 5369-4c97-913c-b78d2ddd833b │ the previous 3nm node. │ │ ├─────┼───────────────────────────────┼────────────────────────────────┼───────┤ │ 3 │ The Shape of Tomorrow's │ The new N2 platform features │ 0.93 │ │ │ Semiconductor Technology - │ GAA nanosheet transistors; │ │ │ │ Semiconductor Digest │ middle-/back-end-of-line │ │ │ │ https://www.semiconductor-dig │ interconnects with the densest │ │ │ │ est.com/the-shape-of-tomorrow │ SRAM macro ever reported │ │ │ │ s-semiconductor-technology/ │ (~38Mb/mm2); and a holistic, │ │ │ │ │ system-technology co-optimized │ │ │ │ │ (STCO) architecture offering │ │ │ │ │ great design flexibility. That │ │ │ │ │ architecture includes a │ │ │ │ │ scalable copper-based │ │ │ │ │ redistribution layer and a │ │ │ │ │ flat passivation layer (for │ │ │ │ │ better performance, robust │ │ │ │ │ CPI, and seamless 3D │ │ │ │ │ integration); and │ │ │ │ │ through-silicon vias, or TSVs. │ │ ├─────┼───────────────────────────────┼────────────────────────────────┼───────┤ │ 4 │ 2 nm process - Wikipedia │ According to the projections │ 0.90 │ │ │ https://en.wikipedia.org/wiki │ contained in the 2021 update │ │ │ │ /2_nm_process │ of the International Roadmap │ │ │ │ │ for Devices and Systems │ │ │ │ │ published by the Institute of │ │ │ │ │ Electrical and Electronics │ │ │ │ │ Engineers (IEEE), a '2.1 nm │ │ │ │ │ node range label' is expected │ │ │ │ │ to have a contacted gate pitch │ │ │ │ │ of 45 nanometers and a │ │ │ │ │ tightest metal pitch of 20 │ │ │ │ │ nanometers. │ │ ├─────┼───────────────────────────────┼────────────────────────────────┼───────┤ │ 5 │ TSMC Boosts 2 nm Yields by │ A key innovation in the N2 │ 0.88 │ │ │ 6%, Passing Savings to │ process is the enhanced design │ │ │ │ Customers | TechPowerUp │ of its GAA nanosheet │ │ │ │ https://www.techpowerup.com/3 │ transistors, which offers │ │ │ │ 29435/tsmc-boosts-2-nm-yields │ improved electrostatic control │ │ │ │ -by-6-passing-savings-to-cust │ and reduced gate leakage │ │ │ │ omers │ compared to 3 nm FinFET │ │ │ │ │ transistors, given that the │ │ │ │ │ gate can be controlled from │ │ │ │ │ all sides. This advancement │ │ │ │ │ enables smaller high-density │ │ │ │ │ transistors to maintain │ │ │ │ │ reliable performance through │ │ │ │ │ better threshold voltage │ │ │ │ │ tuning capabilities. │ │ ├─────┼───────────────────────────────┼────────────────────────────────┼───────┤ │ 6 │ TSMC 2nm, full details │ This 2nm platform technology │ 0.82 │ │ │ revealed-Electronics │ includes new Cu RDLs with flat │ │ │ │ Headlines-EEWORLD │ passivation and TSVs, │ │ │ │ https://en.eeworld.com.cn/mp/ │ optimized holistically with │ │ │ │ Icbank/a391002.jspx │ 3DIC to enable system │ │ │ │ │ integration. │ │ ├─────┼───────────────────────────────┼────────────────────────────────┼───────┤ │ 7 │ TSMC begins quietly volume │ TSMC has quietly revealed that │ 0.97 │ │ │ production of 2nm-class chips │ it had commenced volume │ │ │ │ | Tom's Hardware │ production of chips using its │ │ │ │ https://www.tomshardware.com/ │ N2 (2nm-class) fabrication │ │ │ │ tech-industry/semiconductors/ │ process... 'TSMC's 2nm (N2) │ │ │ │ tsmc-begins-quietly-volume-pr │ technology has started volume │ │ │ │ oduction-of-2nm-class-chips-f │ production in 4Q25 as │ │ │ │ irst-gaa-transistor-for-tsmc- │ planned.' │ │ │ │ claims-up-to-15-percent-impro │ │ │ │ │ vement-at-iso-power │ │ │ ├─────┼───────────────────────────────┼────────────────────────────────┼───────┤ │ 8 │ TSMC's 2nm Yield Rates Surge │ Initial tsmc 2nm yield rates │ 0.75 │ │ │ as Mass Production Ramps Up │ are notably high, reportedly │ │ │ │ in 2026 │ reaching around 70%. Some │ │ │ │ https://heqingele.com/blog/ts │ reports even indicate yields │ │ │ │ mc-2nm-yield-rates-mass-produ │ surpassing 90% for certain │ │ │ │ ction-status-2026/ │ memory products. │ │ ├─────┼───────────────────────────────┼────────────────────────────────┼───────┤ │ 9 │ Unlocking the Future: TSMC's │ On March 31, 2025, TSMC held │ 0.80 │ │ │ Bold Strategy for the 2nm │ an expansion ceremony for its │ │ │ │ Revolution! │ 2nm production facility in │ │ │ │ https://tspasemiconductor.sub │ Kaohsiung, marking a │ │ │ │ stack.com/p/unlocking-the-fut │ significant milestone in │ │ │ │ ure-tsmcs-bold-strategy-cb2 │ Taiwan's semiconductor │ │ │ │ │ advanced manufacturing │ │ │ │ │ expansion. │ │ └─────┴───────────────────────────────┴────────────────────────────────┴───────┘ Gaps ┏━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┓ ┃ Category ┃ Topic ┃ Detail ┃ ┡━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┩ │ source_not_found │ Exact dielectric and gate │ TSMC does not publicly │ │ │ oxide materials used in N2 │ disclose the specific │ │ │ GAA nanosheet transistors │ high-k dielectric │ │ │ │ materials, interfacial │ │ │ │ layer compositions, or work │ │ │ │ function metal chemistries │ │ │ │ used in the N2 gate stack. │ │ │ │ These are considered core │ │ │ │ IP. │ ├──────────────────┼─────────────────────────────┼─────────────────────────────┤ │ source_not_found │ Nanosheet thickness and │ The precise nanometer-scale │ │ │ width tolerances │ dimensions and process │ │ │ │ tolerances (e.g., nanosheet │ │ │ │ thickness variation, │ │ │ │ critical dimension │ │ │ │ uniformity) for N2 GAA │ │ │ │ nanosheets are not publicly │ │ │ │ available. │ ├──────────────────┼─────────────────────────────┼─────────────────────────────┤ │ source_not_found │ Metal interconnect liner │ While Cu RDLs are │ │ │ and barrier materials │ confirmed, the specific │ │ │ │ barrier/liner materials │ │ │ │ (e.g., whether ruthenium or │ │ │ │ cobalt liners replace │ │ │ │ TaN/Ta at this node) are │ │ │ │ not disclosed in public │ │ │ │ sources. │ ├──────────────────┼─────────────────────────────┼─────────────────────────────┤ │ source_not_found │ Doping profiles and implant │ Source/drain doping │ │ │ specifications │ concentrations, implant │ │ │ │ energies, and anneal │ │ │ │ conditions are proprietary │ │ │ │ and not published. │ ├──────────────────┼─────────────────────────────┼─────────────────────────────┤ │ source_not_found │ EUV lithography specifics │ The number of EUV exposures │ │ │ (number of EUV layers, │ per layer, overlay │ │ │ stochastic defect control │ tolerances, and specific │ │ │ methods) │ stochastic control │ │ │ │ approaches are not detailed │ │ │ │ in public TSMC disclosures. │ └──────────────────┴─────────────────────────────┴─────────────────────────────┘ Discovery Events ┏━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━┓ ┃ ┃ Suggested ┃ ┃ ┃ ┃ Type ┃ Researcher ┃ Query ┃ Reason ┃ ┡━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━┩ │ related_research │ arxiv │ TSMC N2 nanosheet │ IEEE IEDM 2024 │ │ │ │ GAA transistor │ papers from TSMC │ │ │ │ gate stack │ may contain more │ │ │ │ materials high-k │ specific │ │ │ │ dielectric IEDM │ materials details │ │ │ │ 2024 │ in the full │ │ │ │ │ published │ │ │ │ │ proceedings not │ │ │ │ │ summarized in │ │ │ │ │ news articles. │ ├──────────────────┼───────────────────┼───────────────────┼───────────────────┤ │ related_research │ database │ TSMC 2nm N2 │ TSMC patent │ │ │ │ process patent │ filings related │ │ │ │ filings nanosheet │ to N2 may reveal │ │ │ │ gate-all-around │ specific │ │ │ │ materials │ materials │ │ │ │ │ choices, │ │ │ │ │ tolerances, and │ │ │ │ │ process │ │ │ │ │ innovations that │ │ │ │ │ are not in press │ │ │ │ │ releases. │ ├──────────────────┼───────────────────┼───────────────────┼───────────────────┤ │ related_research │ arxiv │ gate-all-around │ Academic │ │ │ │ nanosheet │ literature on GAA │ │ │ │ transistor │ nanosheet │ │ │ │ silicon channel │ fabrication may │ │ │ │ thickness │ reveal typical │ │ │ │ variation │ tolerance ranges │ │ │ │ tolerance 2nm │ used at the 2nm │ │ │ │ │ class node even │ │ │ │ │ if not │ │ │ │ │ TSMC-specific. │ ├──────────────────┼───────────────────┼───────────────────┼───────────────────┤ │ related_research │ database │ TechInsights TSMC │ TechInsights │ │ │ │ N2 teardown │ performs physical │ │ │ │ materials │ reverse │ │ │ │ analysis 2025 │ engineering of │ │ │ │ │ chips and may │ │ │ │ │ have detailed N2 │ │ │ │ │ materials │ │ │ │ │ analysis │ │ │ │ │ available through │ │ │ │ │ their │ │ │ │ │ subscription │ │ │ │ │ service. │ └──────────────────┴───────────────────┴───────────────────┴───────────────────┘ Open Questions ┏━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┓ ┃ Priority ┃ Question ┃ Context ┃ ┡━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┩ │ high │ What specific high-k dielectric │ Public sources confirm GAA │ │ │ and metal gate materials does │ nanosheet architecture but do │ │ │ TSMC use in the N2 GAA │ not specify gate dielectric │ │ │ nanosheet gate stack? │ (e.g., HfO2 variants) or work │ │ │ │ function metal compositions │ │ │ │ used to achieve threshold │ │ │ │ voltage tuning. │ ├──────────┼─────────────────────────────────┼─────────────────────────────────┤ │ high │ Has TSMC adopted ruthenium or │ At 20nm metal pitch, │ │ │ other alternative metals for │ traditional TaN/Ta/Cu stacks │ │ │ BEOL interconnect liners in N2 │ face resistance issues; Intel │ │ │ to reduce resistance at tight │ and others have explored Mo and │ │ │ pitches? │ Ru. TSMC's specific choice for │ │ │ │ N2 BEOL is not disclosed in │ │ │ │ public sources. │ ├──────────┼─────────────────────────────────┼─────────────────────────────────┤ │ high │ What is the actual silicon │ GAA nanosheet devices typically │ │ │ nanosheet thickness and stack │ stack 3-4 nanosheets; TSMC has │ │ │ count in TSMC's N2 process? │ not publicly specified │ │ │ │ nanosheet dimensions or stack │ │ │ │ count for N2. │ ├──────────┼─────────────────────────────────┼─────────────────────────────────┤ │ medium │ How does TSMC's N2 defect │ A LinkedIn post references │ │ │ density compare quantitatively │ Tom's Hardware reporting that │ │ │ to N3 at equivalent production │ TSMC disclosed N2 defect │ │ │ maturity? │ density is lower than N3 at the │ │ │ │ same stage of development, but │ │ │ │ specific numbers were not found │ │ │ │ in the gathered sources. │ ├──────────┼─────────────────────────────────┼─────────────────────────────────┤ │ medium │ Will TSMC's N2P (enhanced N2) │ Sources mention N2P is a 5% │ │ │ node incorporate backside power │ speed-enhanced version of N2 │ │ │ delivery network (BSPDN), and │ targeting qualification │ │ │ what materials/process changes │ completion; the SemiAnalysis │ │ │ does that entail? │ report discusses BSPDN as a key │ │ │ │ innovation at 2nm class nodes, │ │ │ │ and its material implications │ │ │ │ differ significantly. │ └──────────┴─────────────────────────────────┴─────────────────────────────────┘ ╭───────────────────────────────── Confidence ─────────────────────────────────╮ │ Overall: 0.42 │ │ Corroborating sources: 9 │ │ Source authority: medium │ │ Contradiction detected: False │ │ Query specificity match: 0.30 │ │ Budget status: spent │ │ Recency: current │ ╰──────────────────────────────────────────────────────────────────────────────╯ ╭──────────────────────────────────── Cost ────────────────────────────────────╮ │ Tokens: 62620 │ │ Iterations: 3 │ │ Wall time: 105.63s │ │ Model: claude-sonnet-4-6 │ ╰──────────────────────────────────────────────────────────────────────────────╯ trace_id: a4bb5b7a-61dd-446b-8c06-06c78de5fef7