13215d7ddb
Issue #46 (Phase A only — Phase B human rating still pending, issue stays open). Adds the data-collection half of the calibration milestone: - scripts/calibration_runner.sh — runs 20 fixed balanced-depth queries across 4 categories (factual, comparative, contradiction-prone, scope-edge), 5 each, capturing per-run logs to docs/stress-tests/M3.3-runs/. - scripts/calibration_collect.py — loads every persisted ResearchResult under ~/.marchwarden/traces/*.result.json and emits a markdown rating worksheet with one row per run. Recovers question text from each trace's start event and category from the run-log filename. - docs/stress-tests/M3.3-rating-worksheet.md — 22 runs (20 calibration + caffeine smoke + M3.2 multi-axis), with empty actual_rating columns for the human-in-the-loop scoring step. - docs/stress-tests/M3.3-runs/*.log — runtime logs from the calibration runner, kept as provenance. Gitignore updated with an exception carving stress-test logs out of the global *.log ignore. Note: M3.1's 4 runs predate #54 (full result persistence) and so are unrecoverable to the worksheet — only post-#54 runs have a result.json sibling. 22 rateable runs is still within the milestone target of 20–30. Phases B (human rating) and C (analysis + rubric + wiki update) follow in a later session. This issue stays open until both are done. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
325 lines
36 KiB
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325 lines
36 KiB
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Researching: What are the precise materials and tolerances in TSMC's 2nm
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process?
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╭─────────────────────────────────── Answer ───────────────────────────────────╮
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│ TSMC's 2nm (N2) process node, which began volume production in Q4 2025, │
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│ introduces several key technical advances, though precise proprietary │
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│ materials specifications and sub-angstrom tolerances are not publicly │
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│ disclosed. What is publicly known: │
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│ │
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│ **Transistor Architecture:** N2 is TSMC's first node to use Gate-All-Around │
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│ (GAA) nanosheet transistors, replacing the FinFET architecture used since │
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│ 2011. The gate surrounds the silicon nanosheet channel on all sides, │
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│ providing superior electrostatic control and reduced gate leakage compared │
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│ to 3nm FinFETs [Sources 10, 13, 21]. │
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│ │
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│ **Process Node Dimensions (IEEE IRDS):** The 2nm node class is projected to │
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│ have a contacted gate pitch of ~45nm and a tightest metal pitch of ~20nm, │
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│ per IEEE International Roadmap for Devices and Systems (2021 update) [Source │
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│ 16]. │
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│ │
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│ **Interconnects:** N2 features copper (Cu)-based redistribution layers │
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│ (RDLs) with flat passivation and through-silicon vias (TSVs), co-optimized │
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│ with 3DIC integration. Middle- and back-end-of-line (MEOL/BEOL) │
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│ interconnects are included, with the densest SRAM macro ever reported at │
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│ approximately 38 Mb/mm² [Sources 4, 21]. │
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│ │
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│ **Performance Metrics (vs. N3E):** 24–35% power reduction OR 15% performance │
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│ improvement at iso-voltage; >1.15x transistor density improvement over N3 │
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│ [Sources 10, 18, 21]. │
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│ │
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│ **Yield:** Initial yields reportedly ~70%, with some memory products │
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│ exceeding 90%. A 6% yield improvement over baseline was reported in late │
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│ 2024 [Sources 13, 14]. │
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│ │
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│ **Applications:** Designed for AI, mobile, and HPC applications. Key │
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│ customers include Apple (A20 chip for iPhone 18 Pro) and NVIDIA [Sources 8, │
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│ 14]. │
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│ │
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│ **Fab Locations:** Primary production in Hsinchu and Kaohsiung, Taiwan; a │
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│ Kaohsiung 2nm facility expansion ceremony was held March 31, 2025 [Source │
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│ 6]. │
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│ │
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│ **Specific proprietary materials** (e.g., exact dielectric compositions, │
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│ gate oxide materials, metal liner chemistries, doping concentrations, and │
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│ nanometer-level tolerances on nanosheet thickness/width) are not publicly │
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│ disclosed by TSMC and were not found in the available evidence. │
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╰──────────────────────────────────────────────────────────────────────────────╯
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Citations
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┏━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━┓
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┃ # ┃ Title / Locator ┃ Excerpt ┃ Conf ┃
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┡━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━┩
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│ 1 │ TSMC shares deep-dive details │ The new production node │ 0.95 │
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│ │ about its cutting edge 2nm │ promises a 24 to 35% power │ │
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│ │ process node at IEDM 2024 — │ reduction or 15% performance │ │
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│ │ 35 percent less power or 15 │ improvement at the same │ │
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│ │ percent more performance | │ voltage, and 1.15X higher │ │
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│ │ Tom's Hardware │ transistor density than the │ │
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│ │ https://www.tomshardware.com/ │ previous 3nm node. │ │
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│ │ tech-industry/tsmc-shares-dee │ │ │
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│ │ p-dive-details-about-its-cutt │ │ │
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│ │ ing-edge-2nm-process-node-at- │ │ │
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│ │ iedm-2024-35-percent-less-pow │ │ │
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│ │ er-or-15-percent-more-perform │ │ │
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│ │ ance │ │ │
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├─────┼───────────────────────────────┼────────────────────────────────┼───────┤
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│ 2 │ IEDM 2024 – TSMC 2nm Process │ The paper states that the │ 0.95 │
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│ │ Disclosure - TechInsights │ process delivers a 30% power │ │
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│ │ https://library.techinsights. │ improvement or 15% performance │ │
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│ │ com/public/hg-asset/f32a0f17- │ gain and >1.15x density versus │ │
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│ │ 5369-4c97-913c-b78d2ddd833b │ the previous 3nm node. │ │
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├─────┼───────────────────────────────┼────────────────────────────────┼───────┤
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│ 3 │ The Shape of Tomorrow's │ The new N2 platform features │ 0.93 │
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│ │ Semiconductor Technology - │ GAA nanosheet transistors; │ │
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│ │ Semiconductor Digest │ middle-/back-end-of-line │ │
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│ │ https://www.semiconductor-dig │ interconnects with the densest │ │
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│ │ est.com/the-shape-of-tomorrow │ SRAM macro ever reported │ │
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│ │ s-semiconductor-technology/ │ (~38Mb/mm2); and a holistic, │ │
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│ │ │ system-technology co-optimized │ │
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│ │ │ (STCO) architecture offering │ │
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│ │ │ great design flexibility. That │ │
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│ │ │ architecture includes a │ │
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│ │ │ scalable copper-based │ │
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│ │ │ redistribution layer and a │ │
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│ │ │ flat passivation layer (for │ │
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│ │ │ better performance, robust │ │
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│ │ │ CPI, and seamless 3D │ │
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│ │ │ integration); and │ │
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│ │ │ through-silicon vias, or TSVs. │ │
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├─────┼───────────────────────────────┼────────────────────────────────┼───────┤
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│ 4 │ 2 nm process - Wikipedia │ According to the projections │ 0.90 │
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│ │ https://en.wikipedia.org/wiki │ contained in the 2021 update │ │
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│ │ /2_nm_process │ of the International Roadmap │ │
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│ │ │ for Devices and Systems │ │
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│ │ │ published by the Institute of │ │
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│ │ │ Electrical and Electronics │ │
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│ │ │ Engineers (IEEE), a '2.1 nm │ │
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│ │ │ node range label' is expected │ │
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│ │ │ to have a contacted gate pitch │ │
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│ │ │ of 45 nanometers and a │ │
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│ │ │ tightest metal pitch of 20 │ │
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│ │ │ nanometers. │ │
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├─────┼───────────────────────────────┼────────────────────────────────┼───────┤
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│ 5 │ TSMC Boosts 2 nm Yields by │ A key innovation in the N2 │ 0.88 │
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│ │ 6%, Passing Savings to │ process is the enhanced design │ │
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│ │ Customers | TechPowerUp │ of its GAA nanosheet │ │
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│ │ https://www.techpowerup.com/3 │ transistors, which offers │ │
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│ │ 29435/tsmc-boosts-2-nm-yields │ improved electrostatic control │ │
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│ │ -by-6-passing-savings-to-cust │ and reduced gate leakage │ │
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│ │ omers │ compared to 3 nm FinFET │ │
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│ │ │ transistors, given that the │ │
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│ │ │ gate can be controlled from │ │
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│ │ │ all sides. This advancement │ │
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│ │ │ enables smaller high-density │ │
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│ │ │ transistors to maintain │ │
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│ │ │ reliable performance through │ │
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│ │ │ better threshold voltage │ │
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│ │ │ tuning capabilities. │ │
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├─────┼───────────────────────────────┼────────────────────────────────┼───────┤
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│ 6 │ TSMC 2nm, full details │ This 2nm platform technology │ 0.82 │
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│ │ revealed-Electronics │ includes new Cu RDLs with flat │ │
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│ │ Headlines-EEWORLD │ passivation and TSVs, │ │
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│ │ https://en.eeworld.com.cn/mp/ │ optimized holistically with │ │
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│ │ Icbank/a391002.jspx │ 3DIC to enable system │ │
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│ │ │ integration. │ │
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├─────┼───────────────────────────────┼────────────────────────────────┼───────┤
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│ 7 │ TSMC begins quietly volume │ TSMC has quietly revealed that │ 0.97 │
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│ │ production of 2nm-class chips │ it had commenced volume │ │
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│ │ | Tom's Hardware │ production of chips using its │ │
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│ │ https://www.tomshardware.com/ │ N2 (2nm-class) fabrication │ │
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│ │ tech-industry/semiconductors/ │ process... 'TSMC's 2nm (N2) │ │
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│ │ tsmc-begins-quietly-volume-pr │ technology has started volume │ │
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│ │ oduction-of-2nm-class-chips-f │ production in 4Q25 as │ │
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│ │ irst-gaa-transistor-for-tsmc- │ planned.' │ │
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│ │ claims-up-to-15-percent-impro │ │ │
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│ │ vement-at-iso-power │ │ │
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├─────┼───────────────────────────────┼────────────────────────────────┼───────┤
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│ 8 │ TSMC's 2nm Yield Rates Surge │ Initial tsmc 2nm yield rates │ 0.75 │
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│ │ as Mass Production Ramps Up │ are notably high, reportedly │ │
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│ │ in 2026 │ reaching around 70%. Some │ │
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│ │ https://heqingele.com/blog/ts │ reports even indicate yields │ │
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│ │ mc-2nm-yield-rates-mass-produ │ surpassing 90% for certain │ │
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│ │ ction-status-2026/ │ memory products. │ │
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├─────┼───────────────────────────────┼────────────────────────────────┼───────┤
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│ 9 │ Unlocking the Future: TSMC's │ On March 31, 2025, TSMC held │ 0.80 │
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│ │ Bold Strategy for the 2nm │ an expansion ceremony for its │ │
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│ │ Revolution! │ 2nm production facility in │ │
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│ │ https://tspasemiconductor.sub │ Kaohsiung, marking a │ │
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│ │ stack.com/p/unlocking-the-fut │ significant milestone in │ │
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│ │ ure-tsmcs-bold-strategy-cb2 │ Taiwan's semiconductor │ │
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│ │ │ advanced manufacturing │ │
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│ │ │ expansion. │ │
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└─────┴───────────────────────────────┴────────────────────────────────┴───────┘
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Gaps
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┏━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┓
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┃ Category ┃ Topic ┃ Detail ┃
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┡━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┩
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│ source_not_found │ Exact dielectric and gate │ TSMC does not publicly │
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│ │ oxide materials used in N2 │ disclose the specific │
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│ │ GAA nanosheet transistors │ high-k dielectric │
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│ │ │ materials, interfacial │
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│ │ │ layer compositions, or work │
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│ │ │ function metal chemistries │
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│ │ │ used in the N2 gate stack. │
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│ │ │ These are considered core │
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│ │ │ IP. │
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├──────────────────┼─────────────────────────────┼─────────────────────────────┤
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│ source_not_found │ Nanosheet thickness and │ The precise nanometer-scale │
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│ │ width tolerances │ dimensions and process │
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│ │ │ tolerances (e.g., nanosheet │
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│ │ │ thickness variation, │
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│ │ │ critical dimension │
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│ │ │ uniformity) for N2 GAA │
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│ │ │ nanosheets are not publicly │
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│ │ │ available. │
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├──────────────────┼─────────────────────────────┼─────────────────────────────┤
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│ source_not_found │ Metal interconnect liner │ While Cu RDLs are │
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│ │ and barrier materials │ confirmed, the specific │
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│ │ │ barrier/liner materials │
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│ │ │ (e.g., whether ruthenium or │
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│ │ │ cobalt liners replace │
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│ │ │ TaN/Ta at this node) are │
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│ │ │ not disclosed in public │
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│ │ │ sources. │
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├──────────────────┼─────────────────────────────┼─────────────────────────────┤
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│ source_not_found │ Doping profiles and implant │ Source/drain doping │
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│ │ specifications │ concentrations, implant │
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│ │ │ energies, and anneal │
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│ │ │ conditions are proprietary │
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│ │ │ and not published. │
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├──────────────────┼─────────────────────────────┼─────────────────────────────┤
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│ source_not_found │ EUV lithography specifics │ The number of EUV exposures │
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│ │ (number of EUV layers, │ per layer, overlay │
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│ │ stochastic defect control │ tolerances, and specific │
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│ │ methods) │ stochastic control │
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│ │ │ approaches are not detailed │
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│ │ │ in public TSMC disclosures. │
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└──────────────────┴─────────────────────────────┴─────────────────────────────┘
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Discovery Events
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┏━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━┓
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┃ ┃ Suggested ┃ ┃ ┃
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┃ Type ┃ Researcher ┃ Query ┃ Reason ┃
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┡━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━┩
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│ related_research │ arxiv │ TSMC N2 nanosheet │ IEEE IEDM 2024 │
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│ │ │ GAA transistor │ papers from TSMC │
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│ │ │ gate stack │ may contain more │
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│ │ │ materials high-k │ specific │
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│ │ │ dielectric IEDM │ materials details │
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│ │ │ 2024 │ in the full │
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│ │ │ │ published │
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│ │ │ │ proceedings not │
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│ │ │ │ summarized in │
|
||
│ │ │ │ news articles. │
|
||
├──────────────────┼───────────────────┼───────────────────┼───────────────────┤
|
||
│ related_research │ database │ TSMC 2nm N2 │ TSMC patent │
|
||
│ │ │ process patent │ filings related │
|
||
│ │ │ filings nanosheet │ to N2 may reveal │
|
||
│ │ │ gate-all-around │ specific │
|
||
│ │ │ materials │ materials │
|
||
│ │ │ │ choices, │
|
||
│ │ │ │ tolerances, and │
|
||
│ │ │ │ process │
|
||
│ │ │ │ innovations that │
|
||
│ │ │ │ are not in press │
|
||
│ │ │ │ releases. │
|
||
├──────────────────┼───────────────────┼───────────────────┼───────────────────┤
|
||
│ related_research │ arxiv │ gate-all-around │ Academic │
|
||
│ │ │ nanosheet │ literature on GAA │
|
||
│ │ │ transistor │ nanosheet │
|
||
│ │ │ silicon channel │ fabrication may │
|
||
│ │ │ thickness │ reveal typical │
|
||
│ │ │ variation │ tolerance ranges │
|
||
│ │ │ tolerance 2nm │ used at the 2nm │
|
||
│ │ │ │ class node even │
|
||
│ │ │ │ if not │
|
||
│ │ │ │ TSMC-specific. │
|
||
├──────────────────┼───────────────────┼───────────────────┼───────────────────┤
|
||
│ related_research │ database │ TechInsights TSMC │ TechInsights │
|
||
│ │ │ N2 teardown │ performs physical │
|
||
│ │ │ materials │ reverse │
|
||
│ │ │ analysis 2025 │ engineering of │
|
||
│ │ │ │ chips and may │
|
||
│ │ │ │ have detailed N2 │
|
||
│ │ │ │ materials │
|
||
│ │ │ │ analysis │
|
||
│ │ │ │ available through │
|
||
│ │ │ │ their │
|
||
│ │ │ │ subscription │
|
||
│ │ │ │ service. │
|
||
└──────────────────┴───────────────────┴───────────────────┴───────────────────┘
|
||
Open Questions
|
||
┏━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┓
|
||
┃ Priority ┃ Question ┃ Context ┃
|
||
┡━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┩
|
||
│ high │ What specific high-k dielectric │ Public sources confirm GAA │
|
||
│ │ and metal gate materials does │ nanosheet architecture but do │
|
||
│ │ TSMC use in the N2 GAA │ not specify gate dielectric │
|
||
│ │ nanosheet gate stack? │ (e.g., HfO2 variants) or work │
|
||
│ │ │ function metal compositions │
|
||
│ │ │ used to achieve threshold │
|
||
│ │ │ voltage tuning. │
|
||
├──────────┼─────────────────────────────────┼─────────────────────────────────┤
|
||
│ high │ Has TSMC adopted ruthenium or │ At 20nm metal pitch, │
|
||
│ │ other alternative metals for │ traditional TaN/Ta/Cu stacks │
|
||
│ │ BEOL interconnect liners in N2 │ face resistance issues; Intel │
|
||
│ │ to reduce resistance at tight │ and others have explored Mo and │
|
||
│ │ pitches? │ Ru. TSMC's specific choice for │
|
||
│ │ │ N2 BEOL is not disclosed in │
|
||
│ │ │ public sources. │
|
||
├──────────┼─────────────────────────────────┼─────────────────────────────────┤
|
||
│ high │ What is the actual silicon │ GAA nanosheet devices typically │
|
||
│ │ nanosheet thickness and stack │ stack 3-4 nanosheets; TSMC has │
|
||
│ │ count in TSMC's N2 process? │ not publicly specified │
|
||
│ │ │ nanosheet dimensions or stack │
|
||
│ │ │ count for N2. │
|
||
├──────────┼─────────────────────────────────┼─────────────────────────────────┤
|
||
│ medium │ How does TSMC's N2 defect │ A LinkedIn post references │
|
||
│ │ density compare quantitatively │ Tom's Hardware reporting that │
|
||
│ │ to N3 at equivalent production │ TSMC disclosed N2 defect │
|
||
│ │ maturity? │ density is lower than N3 at the │
|
||
│ │ │ same stage of development, but │
|
||
│ │ │ specific numbers were not found │
|
||
│ │ │ in the gathered sources. │
|
||
├──────────┼─────────────────────────────────┼─────────────────────────────────┤
|
||
│ medium │ Will TSMC's N2P (enhanced N2) │ Sources mention N2P is a 5% │
|
||
│ │ node incorporate backside power │ speed-enhanced version of N2 │
|
||
│ │ delivery network (BSPDN), and │ targeting qualification │
|
||
│ │ what materials/process changes │ completion; the SemiAnalysis │
|
||
│ │ does that entail? │ report discusses BSPDN as a key │
|
||
│ │ │ innovation at 2nm class nodes, │
|
||
│ │ │ and its material implications │
|
||
│ │ │ differ significantly. │
|
||
└──────────┴─────────────────────────────────┴─────────────────────────────────┘
|
||
╭───────────────────────────────── Confidence ─────────────────────────────────╮
|
||
│ Overall: 0.42 │
|
||
│ Corroborating sources: 9 │
|
||
│ Source authority: medium │
|
||
│ Contradiction detected: False │
|
||
│ Query specificity match: 0.30 │
|
||
│ Budget status: spent │
|
||
│ Recency: current │
|
||
╰──────────────────────────────────────────────────────────────────────────────╯
|
||
╭──────────────────────────────────── Cost ────────────────────────────────────╮
|
||
│ Tokens: 62620 │
|
||
│ Iterations: 3 │
|
||
│ Wall time: 105.63s │
|
||
│ Model: claude-sonnet-4-6 │
|
||
╰──────────────────────────────────────────────────────────────────────────────╯
|
||
|
||
trace_id: a4bb5b7a-61dd-446b-8c06-06c78de5fef7
|